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19-0068; Rev 3; 12/05
KIT ATION EVALU ILABLE AVA
ISDB-T Single-Segment Low-IF Tuners
General Description
The MAX2160/EBG tuner ICs are designed for use in Japanese mobile digital TV (ISDB-T single-segment) applications. The devices directly convert UHF band signals to a low-IF using a broadband I/Q downconverter. The operating frequency range extends from 470MHz to 770MHz. The MAX2160/EBG support both I/Q low-IF interfaces as well as single low-IF interfaces, making the devices universal tuners for various digital demodulator IC implementations. The MAX2160/EBG include an LNA, RF variable-gain amplifiers, I and Q downconverting mixers, low-IF variablegain amplifiers, and bandpass filters providing in excess of 42dB of image rejection. The parts are capable of operating with either high-side or low-side local oscillator (LO) injection. The MAX2160/EBG's variable-gain amplifiers provide in excess of 100dB of gain-control range. The MAX2160/EBG also include fully monolithic VCOs and tank circuits, as well as a complete frequency synthesizer. The devices include a XTAL oscillator as well as a separate TCXO input buffer. The devices operate with XTAL/TCXO oscillators from 13MHz to 26MHz allowing the shared use of a VC-TCXO in cellular handset applications. Additionally, a divider is provided for the XTAL/TCXO oscillator allowing for simple and lowcost interfacing to various channel decoders. The MAX2160/EBG are specified for operation from -40C to +85C and available in a 40-pin thin QFN leadfree plastic package with exposed paddle (EP), and in a lead-free wafer-level package (WLP).
Features
Low Noise Figure: < 4dB Typical High Dynamic Range: -98dBm to 0dBm High-Side or Low-Side LO Injection Integrated VCO and Tank Circuits Low LO Phase Noise: Typical -88dBc/Hz at 10kHz Integrated Frequency Synthesizer Integrated Bandpass Filters 52dB Typical Image Rejection
MAX2160/MAX2160EBG
Single +2.7V to +3.3V Supply Voltage Three Low-Power Modes Two-Wire, I2C*-Compatible Serial Control Interface Very Small Lead-Free WLP Package
Pin Configurations/ Functional Diagrams
GNDTUNE GNDVCO VCCVCO VCOBYP 32 TOP VIEW GNDCP VCCCP CPOUT TEST VTUNE
40 N.C. 1 TCXO 2 XTAL 3 GNDXTAL 4 VCCXTAL 5 XTALOUT 6
39
38
37
36
35
34 TANK
33
31 30 N.C.
FREQUENCY SYNTHESIZER
N.C. 29 VCCBB 28 N.C. 27 QOUT 26 GNDBB 25 IOUT 24 N.C. 23 GC2 22 ENTCXO 21 N.C. 20 VCCFLT
DIV4
ADC
/
Applications
Cell Phone Mobile TVs Personal Digital Assistants (PDAs) Pocket TVs
INTERFACE LOGIC AND CONTROL
VCCDIG 7 SDA 8 SCL 9
MAX2160
PWRDET EP
Ordering Information
PART MAX2160ETL TEMP RANGE -40C to +85C PIN-PACKAGE 40 Thin QFN-EP** (6mm x 6mm) PKG CODE T4066-2
LTC 10
11 N.C.
12 VCCBIAS
13 RFIN
14 SHDN
15 N.C.
16 VCCLNA
17 GC1
18 VCCMX
19 PWRDET
TQFN
40 Thin QFN-EP** MAX2160ETL+ -40C to +85C (6mm x 6mm) MAX2160EBG+ -40C to +85C WLP (3.175mm x 3.175mm)
Pin Configurations/Functional Diagrams continued at end of data sheet.
T4066-2
B08133+1
+Denotes lead-free package. **EP = Exposed paddle.
*Purchase of I2C components from Maxim Integrated Products Inc., or one of its sublicensed Associated Companies, conveys a license under the Philips I2C Patent Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips.
________________________________________________________________ Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim's website at www.maxim-ic.com.
ISDB-T Single-Segment Low-IF Tuners MAX2160/MAX2160EBG
ABSOLUTE MAXIMUM RATINGS
All VCC_ Pins to GND............................................-0.3V to +3.6V All Other Pins to GND.................................-0.3V to (VCC + 0.3V) RFIN, Maximum RF Input Power ....................................+10dBm ESD Rating .............................................................................1kV Short-Circuit Duration IOUT, QOUT, CPOUT, XTALOUT, PWRDET, SDA, TEST, LTC, VCOBYP ...........................................................10s
CAUTION! ESD SENSITIVE DEVICE
Continuous Power Dissipation (TA = +70C) 40-Pin Thin QFN (derate 35.7mW/C above +70C)....2857mW WLP (derate 10.8mW/C above +70C).........................704mW Operating Temperature Range ...........................-40C to +85C Junction Temperature ......................................................+150C Storage Temperature Range .............................-65C to +150C Lead Temperature (soldering, 10s) .................................+300C
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
DC ELECTRICAL CHARACTERISTICS
(MAX2160 EV kit, VCC = +2.7V to +3.3V, VGC1 = VGC2 = 0.3V (maximum gain), no RF input signals at RFIN, baseband I/Os are open circuited and VCO is active with fLO = 767.714MHz, registers set according to the recommended default register conditions of Tables 2-11, TA = -40C to +85C, unless otherwise noted. Typical values are at VCC = +2.85V, TA = +25C, unless otherwise noted.) (Note 1)
PARAMETER SUPPLY Supply Voltage Receive mode, SHDN = VCC , BBL[1:0] = 00 Supply Current (See Tables 15 and 16) Standby mode, bit STBY = 1 Power-down mode, bit PWDN = 1, EPD = 0 Shutdown mode, SHDN = GND ANALOG GAIN-CONTROL INPUTS (GC1, GC2) Input Voltage Range Input Bias Current VCO TUNING VOLTAGE INPUT (VTUNE) Input Voltage Range VTUNE ADC Resolution Input Voltage Range 110 to 111 101 to 110 100 to 101 Reference Ladder Trip Point ADC read bits 011 to 100 010 to 011 001 to 010 000 to 001 LOCK TIME CONSTANT OUTPUT (LTC) Source Current Bit LTC = 0 Bit LTC = 1 1 2 A 0.3 VCC - 0.4 1.9 1.7 1.3 0.9 0.6 0.4 V 3 2.4 bits V 0.4 2.3 V Maximum gain = 0.3V 0.3 -15 2.7 +15 V A 2.7 2.85 44 2 5 0 3.3 53.5 4 40 10 V mA A CONDITIONS MIN TYP MAX UNITS
2
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ISDB-T Single-Segment Low-IF Tuners
DC ELECTRICAL CHARACTERISTICS (continued)
(MAX2160 EV kit, VCC = +2.7V to +3.3V, VGC1 = VGC2 = 0.3V (maximum gain), no RF input signals at RFIN, baseband I/Os are open circuited and VCO is active with fLO = 767.714MHz, registers set according to the recommended default register conditions of Tables 2-11, TA = -40C to +85C, unless otherwise noted. Typical values are at VCC = +2.85V, TA = +25C, unless otherwise noted.) (Note 1)
PARAMETER SHUTDOWN CONTROL (SHDN) Input-Logic-Level High Input-Logic-Level Low 2-WIRE SERIAL INPUTS (SCL, SDA) Clock Frequency Input-Logic-Level High Input-Logic-Level Low Input Leakage Current 2-WIRE SERIAL OUTPUT (SDA) Output-Logic-Level Low 0.2 V Digital inputs = GND or VCC 0.1 0.7 x VCC 0.3 x VCC 1 400 kHz V V A 0.7 x VCC 0.3 x VCC V V CONDITIONS MIN TYP MAX UNITS
MAX2160/MAX2160EBG
AC ELECTRICAL CHARACTERISTICS
(MAX2160 EV kit, VCC = +2.7V to +3.3V, fRF = 767.143MHz, fLO = 767.714MHz, fBB = 571kHz, fXTAL = 16MHz, VGC1 = VGC2 = 0.3V (maximum gain), registers set according to the recommended default register conditions of Tables 2-11, RF input signals as specified, baseband output load as specified, TA = -40C to +85C, unless otherwise noted. Typical values are at VCC = +2.85V, TA = +25C, unless otherwise noted.) (Note 1)
PARAMETER MAIN SIGNAL PATH PERFORMANCE Input Frequency Range Minimum Input Signal Maximum Voltage Gain Minimum Voltage Gain RF Gain-Control Range Baseband Gain-Control Range In-Band Input IP3 Out-of-Band Input IP3 Input IP2 Input P1dB Noise Figure Image Rejection Minimum RF Input Return Loss LO Leakage at RFIN IF POWER DETECTOR Resolution Minimum RF Attack Point Maximum RF Attack Point Detector Bandwidth Output Compliance Range Response Time C14 = 10nF Power at RFIN Power at RFIN 3dB RF bandwidth 0.3 0.1 3 -62 -48 35 2.7 bits dBm dBm MHz V ms fRF = 620MHz, 50 system 13-segment input CW tone, VGC1 = VGC2 = 0.3V, bit MOD = 1 CW tone, VGC1 = VGC2 = 2.7V, bit MOD = 0 0.3V < VGC1 < 2.7V 0.3V < VGC2 < 2.7V (Note 2) (Note 3) (Note 4) CW tone, VGC1 = VGC2 = 2.7V, bit MOD = 0 VGC1 = VGC2 = 0.3V, TA = +25C (Note 5) 42 38 57 43 67 +4 +16.7 +16 0 3.8 52 14 -100 5 104 2 470 -98 770 MHz dBm dB dB dB dB dBm dBm dBm dBm dB dB dB dBm CONDITIONS MIN TYP MAX UNITS
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ISDB-T Single-Segment Low-IF Tuners MAX2160/MAX2160EBG
AC ELECTRICAL CHARACTERISTICS (continued)
(MAX2160 EV kit, VCC = +2.7V to +3.3V, fRF = 767.143MHz, fLO = 767.714MHz, fBB = 571kHz, fXTAL = 16MHz, VGC1 = VGC2 = 0.3V (maximum gain), registers set according to the recommended default register conditions of Tables 2-11, RF input signals as specified, baseband output load as specified, TA = -40C to +85C, unless otherwise noted. Typical values are at VCC = +2.85V, TA = +25C, unless otherwise noted.) (Note 1)
PARAMETER LOW-IF BANDPASS FILTERS Center Frequency Frequency Response (Note 5) Group Delay Variation Nominal Output-Voltage Swing I/Q Amplitude Imbalance I/Q Quadrature Phase Imbalance Output Gain Step I/Q Output Impedance FREQUENCY SYNTHESIZER RF-Divider Frequency Range RF-Divider Range (N) Reference-Divider Frequency Range Reference-Divider Range (R) Phase-Detector Comparison Frequency PLL-Referred Phase Noise Floor Comparison Frequency Spurious Products TA = +25C, fCOMP = 285.714kHz Bit EPB = 1 Bits CP[1:0] = 00 Charge-Pump Output Current (Note 5) Bits CP[1:0] = 01 Bits CP[1:0] = 10 Bits CP[1:0] = 11 Charge-Pump Compliance Range Charge-Pump Source/Sink Current Matching 10% variation from current at VTUNE = 1.35V VTUNE = 1.35V 1.25 1.75 2.10 2.50 0.4 -10 470 829 13 22 1/7 -155 -52 1.5 2.0 2.5 3 1.75 2.25 2.90 3.50 2.2 +10 V % mA 770 5374 26 182 4/7 MHz dBc/Hz dBc MHz MHz Bit MOD transition from 0 to 1 Real ZO +7 30 380kHz offset from center frequency 1.3MHz Up to 1dB bandwidth RLOAD = 10k || 10pF (Note 6) -6 -36 100 0.5 1.5 2 571 -1.5 kHz dB ns VP-P dB deg dB CONDITIONS MIN TYP MAX UNITS
BASEBAND OUTPUT CHARACTERISTICS
4
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ISDB-T Single-Segment Low-IF Tuners
AC ELECTRICAL CHARACTERISTICS (continued)
(MAX2160 EV kit, VCC = +2.7V to +3.3V, fRF = 767.143MHz, fLO = 767.714MHz, fBB = 571kHz, fXTAL = 16MHz, VGC1 = VGC2 = 0.3V (maximum gain), registers set according to the recommended default register conditions of Tables 2-11, RF input signals as specified, baseband output load as specified, TA = -40C to +85C, unless otherwise noted. Typical values are at VCC = +2.85V, TA = +25C, unless otherwise noted.) (Note 1)
PARAMETER Guaranteed VCO Frequency Range Guaranteed LO Frequency Range Tuning Voltage Range fOFFSET = 1kHz LO Phase Noise 0.4V < VTUNE < 2.3V, TA = -40C to +85C fOFFSET = 10kHz fOFFSET = 100kHz fOFFSET = 1MHz XTAL OSCILLATOR INPUT (TCXO AND XTAL) XTAL Oscillator Frequency Range XTAL Minimum Negative Resistance XTAL Nominal Input Capacitance TCXO Input Level TCXO Minimum Input Impedance REFERENCE OSCILLATOR BUFFER OUTPUT (XTALOUT) Output Frequency Range Output-Buffer Divider Range Output-Voltage Swing Output Load Output Duty Cycle Output Impedance 1 1 0.7 200 || 4 50 160 26 26 VP-P k || pF % MHz AC-coupled sine-wave input 0.4 10 Parallel resonance mode crystal 16MHz < fXTAL < 18MHz (Note 5) 13 885 13.3 1.5 26 MHz pF VP-P k CONDITIONS MIN TYP MAX UNITS
MAX2160/MAX2160EBG
VOLTAGE-CONTROLLED OSCILLATOR AND LO GENERATION TA = -40C to +85C TA = -40C to +85C 1880 470 0.4 -80 -87.5 -107 -128 dBc/Hz 3080 770 2.3 MHz MHz V
Note 1: Min and max values are production tested at TA = +25C and +85C. Min and max limits at TA = -40C are guaranteed by design and characterization. Default register settings are not production tested; load all registers no sooner than 100s after power-up. Note 2: In-band IIP3 is measured with two tones at fLO - 100kHz and fLO - 200kHz at a power level of -23dBm/tone. GC1 is set for maximum attenuation (VGC1 = 2.7V) and GC2 is adjusted to achieve 250mVP-P/tone at the I/Q outputs for an input desired level of -23dBm. Note 3: Out-of-band IIP3 is measured with two tones at fRF + 6MHz and fRF + 12MHz at a power level of -15dBm/tone. GC1 is set for maximum attenuation (VGC1 = 2.7V) and GC2 is adjusted to achieve 0.5VP-P at the I/Q outputs for an input desired level of -50dBm. fRF is set to 767MHz + 1/7MHz = 767.143MHz. Note 4: GC1 is set for maximum attenuation (VGC1 = 2.7V). GC2 is adjusted to give the nominal I/Q output voltage level (0.5VP-P) for a -50dBm desired tone at fRF = 550MHz. Two tones, 220MHz and 770MHz at -15dBm/tone, are then injected and the 571kHz IM2 levels are measured (with a 550.571MHz LO) at the I/Q outputs and IP2 is then calculated. Note 5: Guaranteed by design and characterization. Note 6: Guaranteed and tested at TA = +25C and +85C only.
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ISDB-T Single-Segment Low-IF Tuners MAX2160/MAX2160EBG
Typical Operating Characteristics
(MAX2160 EV kit, TQFN package, VCC = +2.85V, default register settings, VGC1 = VCG2 = 0.3V, VIOUT = VQOUT = 0.5VP-P, fLO = 767.714MHz, TA = +25C, unless otherwise noted.)
RECEIVE-MODE SUPPLY CURRENT vs. SUPPLY VOLTAGE
MAX2160 toc01
SHUTDOWN-MODE SUPPLY CURRENT vs. SUPPLY VOLTAGE
0.9 0.8 SUPPLY CURRENT (A) 0.7 GAIN (dB) 0.6 0.5 0.4 0.3 0.2 0.1 0 TA = +25C TA = -40C 109 108 107 2.7 2.8 2.9 3.0 3.1 3.2 3.3 470 TA = +85C
MAX2160 toc02
VOLTAGE GAIN vs. FREQUENCY
MAX2160 toc03
50 49 48 SUPPLY CURRENT (mA) 47 46 45 44 43 42 41 40 2.7 2.8 2.9 3.0 3.1 3.2 TA = -40C BBL[1:0] = 00 TA = +25C TA = +85C
1.0
113 112 111 110
3.3
520
570
620
670
720
770
SUPPLY VOLTAGE (V)
SUPPLY VOLTAGE (V)
FREQUENCY (MHz)
RELATIVE GC1 GAIN RANGE vs. GC1 VOLTAGE
MAX2160 toc04
RELATIVE GC2 GAIN RANGE vs. GC2 VOLTAGE
MAX2160 toc05
NOISE FIGURE vs. FREQUENCY
9 8 NOISE FIGURE (dB) 7 6 5 4 3 TA = +25C TA = -40C TA = +85C
MAX2160 toc06
10 0 RELATIVE GC2 GAIN RANGE (dB) -10 -20 -30 -40 -50 -60 -70 -80 FIXED VGC1 0 0.5 1.0 1.5 VGC2 (V) 2.0 2.5 TA = -40C TA = +85C TA = +25C
10
0 RELATIVE GC1 GAIN RANGE (dB) -10 TA = +85C -20 -30 TA = +25C -40 FIXED VGC2 -50 0 0.5 1.0 1.5 VGC1 (V) 2.0 2.5 TA = -40C
2 1 0 3.0 470
3.0
520
570
620
670
720
770
FREQUENCY (MHz)
NOISE FIGURE vs. INPUT POWER
MAX2160 toc07
IN-BAND IIP3 vs. INPUT POWER
CLOSED-LOOP POWER CONTROL fLO = 767.714MHz f1 = fLO - 100kHz, f2 = fLO - 200kHz
MAX2160 toc08
INPUT RETURN LOSS vs. FREQUENCY
5 INPUT RETURN LOSS (dB) 10 15 20 25 30 35 40 45
MAX2160 toc09
60 CLOSED-LOOP POWER CONTROL 50 NOISE FIGURE (dB) 40 30 20 10 0 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 0 INPUT POWER (dBm)
20 0 IN-BAND IIP3 (dBm) -20 -40 -60 -80 -100 -120 -100 -80 -60 -40 -20 0 INPUT POWER (dBm)
0
50 470 520 570 620 670 720 770 FREQUENCY (MHz)
6
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ISDB-T Single-Segment Low-IF Tuners
Typical Operating Characteristics (continued)
(MAX2160 EV kit, TQFN package, VCC = +2.85V, default register settings, VGC1 = VCG2 = 0.3V, VIOUT = VQOUT = 0.5VP-P, fLO = 767.714MHz, TA = +25C, unless otherwise noted.)
IF FILTER FREQUENCY RESPONSE
MAX2160 toc10 MAX2160 toc11
MAX2160/MAX2160EBG
LO-TO-RFIN LEAKAGE vs. FREQUENCY
-105 -106 LO-TO-RFIN LEAKAGE (dBm) -107 -108 -109 -110 -111 -112 -113 -114 -115 470 520 570 620 670 720 770 FREQUENCY (MHz) -60 0 0 -10 NORMALIZED GAIN (dB) -20 -30 -40 -50
IF FILTER PASSBAND FREQUENCY RESPONSE
-1 -2 NORMALIZED GAIN (dB) -3 -4 -5 -6 -7 -8 -9 -10
MAX2160 toc12
0
250
500
750
1000
1250
1500
100 200 300 400 500 600 700 800 900 10001100 FREQUENCY (kHz)
FREQUENCY (kHz)
GROUP-DELAY VARIATION vs. BASEBAND FREQUENCY
MAX2160 toc13
IF FILTER 3dB FREQUENCY vs. TEMPERATURE
MAX2160 toc14
PHASE NOISE AT 10kHz OFFSET vs. CHANNEL FREQUENCY
PHASE NOISE AT 10kHz OFFSET (dBc/Hz) -82 -84 -86 -88 -90 -92 -94 -96 -98 -100 470 520 570 620 670 720 770
MAX2160 toc16
1000 800 GROUP-DELAY VARIATION (ns) 600 400 200 0 -200 -400 -600 -800 -1000
5 NORMALIZED 3dB FREQUENCY (%) 4 3 2 1 0 -1 -2 -3 -4 -5 NORMALIZED TO TA = +25C -40 -20 0 20 40 60 80 UPPER 3dB CUTOFF LOWER 3dB CUTOFF
-80
200 300 400 500 600 700 800 900 1000 FREQUENCY (kHz)
100
TEMPERATURE (C)
CHANNEL FREQUENCY (MHz)
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ISDB-T Single-Segment Low-IF Tuners MAX2160/MAX2160EBG
Typical Operating Characteristics (continued)
(MAX2160 EV kit, TQFN package, VCC = +2.85V, default register settings, VGC1 = VCG2 = 0.3V, VIOUT = VQOUT = 0.5VP-P, fLO = 767.714MHz, TA = +25C, unless otherwise noted.)
TUNING VOLTAGE vs. VCO FREQUENCY
VCO 1, SB 0-7 VCO 2, SB 0-7 VCO 3, SB 0-7 VCO 4, SB 0-7
MAX2160 toc15
3.0 2.5 2.0 VTUNE (V) 1.5 1.0 0.5 0 350 400 450 500 550 600 VCO FREQUENCY (MHz) 650 700 750 800
850
PHASE NOISE vs. OFFSET FREQUENCY
-60 -70 PHASE NOISE (dBc/Hz) -80 -90 -100 -110 -120 -130 -140 -150 1 10 100 1000 OFFSET FREQUENCY (kHz) fLO = 575.714MHz (VCO 2, SB1)
MAX2160 toc17
POWER-DETECTOR RESPONSE TIME
MAX2160 toc18
-50
B
A
A: LOW = -60dBm RF INPUT POWER HIGH = -20dBm RF INPUT POWER B: POWER-DETECTOR OUTPUT VOLTAGE, 0.5V/div, CLOSED-LOOP POWER-CONTROL DEFAULT ATTACK POINT 0.01F LOOP CAPACITOR 200s/div
8
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ISDB-T Single-Segment Low-IF Tuners
Pin Description
PIN TQFN 1, 11, 15, 21, 24, 28, 30, 31 2 BUMP NO. WLP 29, 33, 34, 35, 36, 45, 46 2 NAME N.C. DESCRIPTION No Connection. Connect to the PC board ground plane. High-Impedance Buffer for External TCXO. When ENTCXO is pulled high, this input is enabled for use with an external TCXO and the internal crystal oscillator is disabled. Requires a DC-blocking capacitor. Crystal-Oscillator Interface. When ENTCXO is pulled low, this input is enabled for use with an external parallel resonance mode crystal. See the Typical Operating Circuit. Crystal-Oscillator Circuit Ground. Connect to the PC board ground plane. DC Power Supply for Crystal-Oscillator Circuits. Connect to a +2.85V low-noise supply. Bypass to GND with a 100pF capacitor connected as close to the pin as possible. Do not share capacitor ground vias with other ground connections. Crystal Oscillator Buffer Output. A DC-blocking capacitor must be used when driving external circuitry. DC Power Supply for Digital Logic Circuits. Connect to a +2.85V low-noise supply. Bypass to GND with a 100pF capacitor connected as close to the pin as possible. Do not share capacitor ground vias with other ground connections. 2-Wire Serial Data Interface. Requires a pullup resistor to VCC. 2-Wire Serial Clock Interface. Requires a pullup resistor to VCC. PLL Lock Time Constant. LTC sources current to an external charging capacitor to set the time constant for the VCO autoselect (VAS) function. See the Loop Time Constant Pin section in the Applications Information. DC Power Supply for Bias Circuits. Connect to a +2.85V low-noise supply. Bypass to GND with a 100pF capacitor connected as close to the pin as possible. Do not share capacitor ground vias with other ground connections. Wideband 50 RF Input. Connect to an RF source through a DC-blocking capacitor. Device Shutdown. Logic-low turns off the entire device including the 2-wire compatible bus. SHDN overrides all software shutdown modes. DC Power Supply for LNA. Connect to a +2.85V low-noise supply. Bypass to GND with a 100pF capacitor connected as close to the pin as possible. Do not share capacitor ground vias with other ground connections. RF Gain-Control Input. High-impedance analog input, with a 0.3V to 2.7V operating range. VGC1 = 0.3V corresponds to the maximum gain setting. DC Power Supply for RF Mixer Circuits. Connect to a +2.85V low-noise supply. Bypass to GND with a 100pF capacitor connected as close to the pin as possible. Do not share capacitor ground vias with other ground connections. Power-Detector Output. See the IF Power Detector section in the Applications Information.
MAX2160/MAX2160EBG
TCXO
3 4 5
11 -- 12
XTAL GNDXTAL VCCXTAL
6
4
XTALOUT
7 8 9 10
5 14 7 19
VCCDIG SDA SCL LTC
12 13 14
9 17 22
VCCBIAS RFIN SHDN
16
24
VCCLNA
17
25
GC1
18
28
VCCMX
19
38
PWRDET
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ISDB-T Single-Segment Low-IF Tuners MAX2160/MAX2160EBG
Pin Description (continued)
PIN TQFN 20 BUMP NO. WLP 39 NAME DESCRIPTION DC Power Supply for Baseband Filter Circuits. Connect to a +2.85V low-noise supply. Bypass to GND with a 100pF capacitor connected as close to the pin as possible. Do not share capacitor ground vias with other ground connections. XTAL/TCXO Select. Logic-high enables the TCXO input and disables the XTAL input. Logic-low disables the TCXO input and enables the XTAL input. This pin is internally pulled up to VCC. Baseband Gain-Control Input. High-impedance analog input, with a 0.3V to 2.7V operating range. VGC2 = 0.3V corresponds to the maximum gain setting. In-Phase Low-IF Output. Requires a DC-blocking capacitor. Ground for Baseband Circuits. Connect to the PC board ground plane. Quadrature Low-IF Output. Requires a DC-blocking capacitor. DC Power Supply for Baseband Circuits. Connect to a +2.85V low-noise supply. Bypass to GND with a 100pF capacitor connected as close to the pin as possible. Do not share capacitor ground vias with other ground connections. Internal VCO Bias Bypass. Bypass directly to GNDVCO with a 470nF capacitor connected as close to the pin as possible. Do not share capacitor ground vias with other ground connections. See the Layout Considerations section. DC Power Supply for VCO Circuits. Connect to a +2.85V low-noise supply. Bypass directly to GNDVCO with a 100pF capacitor connected as close to the pin as possible. Do not share capacitor ground vias with other ground connections. VCO Circuit Ground. Connect to the PC board ground plane. See the Layout Considerations section. High-Impedance VCO Tune Input. Connect the PLL loop filter output directly to this pin with the shortest connection as possible. Ground for VTUNE. Connect to the PC board ground plane. See the Layout Considerations section. Test Output. Used as a test output for various internal blocks. See Table 2. Charge-Pump Output. Connect this output to the PLL loop filter input with the shortest connection possible. DC Power Supply for Charge-Pump Circuits. Connect to a +2.85V low-noise supply. Bypass to GND with a 100pF capacitor connected as close to the pin as possible. Do not share capacitor ground vias with other ground connections. Charge-Pump Circuit Ground. Connect to the PC board ground plane. See the Layout Considerations section. Exposed Paddle. Solder evenly to the board's ground plane for proper operation. Ground. Connect to the PC board ground plane. Ground for LNA. Connect to ground with trace.
VCCFLT
22
37
ENTCXO
23 25 26 27 29
47 44 -- 43 41
GC2 IOUT GNDBB QOUT VCCBB
32
30
VCOBYP
33
26
VCCVCO
34 35 36 37 38
23 32 20 18 16
GNDVCO VTUNE GNDTUNE TEST CPOUT
39
10
VCCCP
40 EP -- --
1 -- 3, 6, 8, 13, 15, 27, 31, 40, 42 21
GNDCP GND GND GNDLNA
10
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ISDB-T Single-Segment Low-IF Tuners
Detailed Description
All registers must be written after power-up and no earlier than 100s after power-up. ble registers include a test register, a PLL register, a VCO register, a control register, a XTAL divide register, an R-divider register, and two N-divider registers. The read-only registers include two status registers.
MAX2160/MAX2160EBG
Register Descriptions
The MAX2160/EBG include eight programmable registers and two read-only registers. The eight programma-
Table 1. Register Configuration
MSB REGISTER NUMBER 1 2 3 4 5 6 7 8 9 10 REGISTER NAME TEST PLL VCO CONTROL XTAL DIVIDE R-DIVIDER N-DIVIDER MSB N-DIVIDER LSB STATUS BYTE-1 STATUS BYTE-2 READ/ WRITE WRITE WRITE WRITE WRITE WRITE WRITE WRITE WRITE READ READ REGISTER ADDRESS D7 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 -- -- TUN2 CP1 VCO1 MOD XD4 R7 N12 N4 X VCO1 D6 TUN1 CP0 VCO0 BBL1 XD3 R6 N11 N3 X VCO0 D5 TUN0 CPS VSB2 BBL0 XD2 R5 N10 N2 X VSB2 DATA BYTE D4 FLTS EPB VSB1 HSLS XD1 R4 N9 N1 CP1 VSB1 D3 MXSD RPD VSB0 PD2 XD0 R3 N8 N0 CP0 VSB0 D2 D2 NPD ADL PD1 PWDN R2 N7 X PWR ADC2 D1 D1 TON ADE PD0 STBY R1 N6 X VASA ADC1 D0 D0 VAS LTC EPD QOFF R0 N5 X VASE ADC0 LSB
Table 2. Test Register
BIT NAME BIT LOCATION (0 = LSB) RECOMMENDED DEFAULT FUNCTION Set the baseband bandpass filter center frequency. This filter's center frequency is trimmed at the factory, but may be manually adjusted by clearing the FLTS bit and programming the TUN[2:0] bits as follows: 000 = 0.75 x fO 001 = 0.80 x fO 010 = 0.86 x fO 011 = 0.92 x fO 100 = fO (nominal center frequency of 571kHz) 101 = 1.08 x fO 110 = 1.19 x fO 111 = 1.32 x fO Selects which registers set the baseband bandpass filter center frequency. 1 = selects internal factory-set register 0 = selects manual trim register TUN[2:0]
TUN[2:0]
7, 6, 5
000
FLTS
4
1
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ISDB-T Single-Segment Low-IF Tuners MAX2160/MAX2160EBG
Table 2. Test Register (continued)
BIT NAME BIT LOCATION (0 = LSB) 3 RECOMMENDED DEFAULT 0 FUNCTION Used for factory trimming of the baseband filters. 1 = disables the quadrature mixers for filter tuning 0 = enables the quadrature mixers Control diagnostic features as follows: 000 = normal operation 001 = force charge-pump source current 010 = force charge-pump sink current 011 = force charge-pump high-impedance state 100 = power-detector RMS voltage at PWRDET 101 = N-divider output at TEST pin 110 = R-divider output at TEST pin 111 = local oscillator output at TEST pin
MXSD
D[2:0]
2, 1, 0
000
Table 3. PLL Register
BIT NAME BIT LOCATION (0 = LSB) RECOMMENDED DEFAULT Set the charge-pump current. 00 = 1.5mA 01 = 2mA 10 = 2.5mA 11 = 3mA Sets the charge-pump current selection mode between automatic and manual. 0 = charge-pump current is set manually through the CP[1:0] bits 1 = charge-pump current is automatically selected based on ADC read values in both VAS and manual VCO selection modes Controls the charge-pump prebias function. 0 = disables the charge-pump prebias function 1 = enables the charge-pump prebias function Sets the prebias on-time control from reference divider. 0 = 280ns 1 = 650ns Sets the prebias on-time control from VCO/LO divider. 0 = 500ns 1 = 1000ns Sets the charge-pump on-time control. 0 = 2.5ns 1 = 5ns Controls the VCO autoselect (VAS) function. 0 = disables the VCO autoselect function and allows manual VCO selection through the VCO[1:0] and VSB[2:0] bits 1 = enables the on-chip VCO autoselect state machine FUNCTION
CP[1:0]
7, 6
11
CPS
5
1
EPB
4
1
RPD
3
0
NPD
2
0
TON
1
0
VAS
0
1
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ISDB-T Single-Segment Low-IF Tuners MAX2160/MAX2160EBG
Table 4. VCO Register
BIT NAME BIT LOCATION (0 = LSB) RECOMMENDED DEFAULT FUNCTION Control which VCO is activated when using manual VCO programming mode. This will also serve as the starting point for the VCO autoselect mode. 00 = select VCO 0 01 = select VCO 1 10 = select VCO 2 11 = select VCO 3 Select a particular sub-band for each of the on-chip VCOs. Together with the VCO[2:0] bits a manual selection of a VCO and a sub-band can be made. This will also serve as the starting point for the VCO autoselect mode. 000 = select sub-band 0 001 = select sub-band 1 010 = select sub-band 2 011 = select sub-band 3 100 = select sub-band 4 101 = select sub-band 5 110 = select sub-band 6 111 = select sub-band 7 Enables or disables the VCO tuning voltage ADC latch when the VCO autoselect mode (VAS) is disabled. 0 = disables the ADC latch 1 = latches the ADC value Enables or disables VCO tuning voltage ADC read when the VCO autoselect mode (VAS) is disabled. 0 = disables ADC read 1 = enables ADC read Sets the source current for the VAS time constant. 0 = 1A 1 = 2A
VCO[1:0]
7, 6
11
VSB[2:0]
5, 4, 3
011
ADL
2
0
ADE
1
0
LTC
0
0
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ISDB-T Single-Segment Low-IF Tuners MAX2160/MAX2160EBG
Table 5. Control Register
BIT NAME BIT LOCATION (0 = LSB) 7 RECOMMENDED DEFAULT 0 FUNCTION Sets the modulation mode and the baseband gain step. 0 = selects QAM mode and disables the 7dB gain step 1 = selects QPSK mode and adds 7dB of gain in the baseband stages Set the bias current for the baseband circuits to provide for fine linearity adjustments. 00 = lower linearity 01 = nominal linearity 10 = medium linearity 11 = high linearity Selects between high-side and low-side LO injection. 0 = low-side injection 1 = high-side injection Set the AGC attack point (at RFIN). 000 = -62dBm 001 = -60dBm 010 = -58dBm 011 = -56dBm 100 = -54dBm 101 = -52dBm 110 = -50dBm 111 = -48dBm Enables or disables the power-detector circuit. 0 = disables the power-detector circuit for low-current mode 1 = enables the power-detector circuit
MOD
BBL[1:0]
6, 5
10
HSLS
4
1
PD[2:0]
3, 2, 1
011
EPD
0
0
14
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ISDB-T Single-Segment Low-IF Tuners MAX2160/MAX2160EBG
Table 6. XTAL Divide
BIT NAME BIT LOCATION (0 = LSB) RECOMMENDED DEFAULT FUNCTION Set the crystal divider ratio for XTALOUT. 00000 = XTALOUT buffer disabled (off) 00001 = divide-by-1 00010 = divide-by-2 00011 = divide-by-3 00100 = divide-by-4 00101 through 11110 = all divide values from 3 (00101) to 30 (11110) 11111 = divide-by-31 Software power-down control. 0 = normal operation 1 = shuts down the entire chip but leaves the 2-wire bus active and maintains the current register states Software standby control. 0 = normal operation 1 = disables the signal path and frequency synthesizer leaving only the 2-wire bus, crystal oscillator, XTALOUT buffer, and XTALOUT buffer divider active Enables and disables the Q-channel output. 0 = Q channel enabled 1 = Q channel disabled
XD[4:0]
7-3
00001
PWDN
2
0
STBY
1
0
QOFF
0
0
Table 7. R-Divider Register
BIT NAME R[7:0] BIT LOCATION (0 = LSB) 7-0 RECOMMENDED DEFAULT 0x38 FUNCTION Set the PLL reference-divider (R) number. Default R-divider value is 56 decimal. R can range from 22 to 182 decimal.
Table 8. N-Divider MSB Register
BIT NAME N[12:5] BIT LOCATION (0 = LSB) 7-0 RECOMMENDED DEFAULT 0x53 FUNCTION Set the most significant bits of the PLL integer-divider number (N). Default integer-divider value is N = 2687 decimal. N can range from 829 to 5374.
Table 9. N-Divider LSB Register
BIT NAME N[4:0] X BIT LOCATION (0 = LSB) 7-3 2, 1, 0 RECOMMENDED DEFAULT 11111 X FUNCTION Set the least significant bits of the PLL integer-divider number (N). Default integer-divider value is N = 2687 decimal. N can range from 829 to 5374. Unused.
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ISDB-T Single-Segment Low-IF Tuners MAX2160/MAX2160EBG
Table 10. Status Byte-1 Register
BIT NAME X CP[1:0] PWR BIT LOCATION (0 = LSB) 7, 6, 5 4, 3 2 Unused. Reflect the charge-pump current setting. See Table 3 for CP[1:0] definition. Logic-high indicates power has been cycled, but the device has the default programming. A STOP condition while in read mode resets this bit. Indicates whether VCO automatic selection was successful. 0 = indicates the autoselect function is disabled or unsuccessful VCO selection 1 = indicates successful VCO automatic selection Status indicator for the autoselect function. 0 = indicates the autoselect function is active 1 = indicates the autoselect process is inactive FUNCTION
VASA
1
VASE
0
Table 11. Status Byte-2 Register
BIT NAME VCO[1:0] BIT LOCATION (0 = LSB) 7, 6 FUNCTION Indicate which VCO has been selected by either the autoselect state machine or by manual selection when the VAS state machine is disabled. See Table 4 for VCO[1:0] definition. Indicate which sub-band of a particular VCO has been selected by either the autoselect state machine or by manual selection when the VAS state machine is disabled. See Table 4 for VSB[2:0] definition. Indicate the 3-bit ADC conversion of the VCO tuning voltage (VTUNE).
VSB[2:0] ADC[2:0]
5, 4, 3 2, 1, 0
2-Wire Serial Interface
The MAX2160/EBG uses a 2-wire I2C-compatible serial interface consisting of a serial-data line (SDA) and a serial-clock line (SCL). SDA and SCL facilitate bidirectional communication between the MAX2160/EBG and the master at clock frequencies up to 400kHz. The master initiates a data transfer on the bus and generates the SCL signal to permit data transfer. The MAX2160/EBG behave as a slave device that transfers and receives data to and from the master. SDA and SCL must be pulled high with external pullup resistors (1k or greater) for proper bus operation. One bit is transferred during each SCL clock cycle. A minimum of nine clock cycles is required to transfer a byte in or out of the MAX2160/EBG (8 bits and an ACK/NACK). The data on SDA must remain stable during the high period of the SCL clock pulse. Changes in SDA while SCL is high and stable are considered con-
trol signals (see the START and STOP Conditions section). Both SDA and SCL remain high when the bus is not busy. START and STOP Conditions The master initiates a transmission with a START condition (S), which is a high-to-low transition on SDA while SCL is high. The master terminates a transmission with a STOP condition (P), which is a low-to-high transition on SDA while SCL is high. Acknowledge and Not-Acknowledge Conditions Data transfers are framed with an acknowledge bit (ACK) or a not-acknowledge bit (NACK). Both the master and the MAX2160/EBG (slave) generate acknowledge bits. To generate an acknowledge, the receiving device must pull SDA low before the rising edge of the acknowledge-related clock pulse (ninth pulse) and keep it low during the high period of the clock pulse.
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ISDB-T Single-Segment Low-IF Tuners
To generate a not-acknowledge condition, the receiver allows SDA to be pulled high before the rising edge of the acknowledge-related clock pulse, and leaves SDA high during the high period of the clock pulse. Monitoring the acknowledge bits allows for detection of unsuccessful data transfers. An unsuccessful data transfer happens if a receiving device is busy or if a system fault has occurred. In the event of an unsuccessful data transfer, the bus master must reattempt communication at a later time. Slave Address The MAX2160/EBG have a 7-bit slave address that must be sent to the device following a START condition to initiate communication. The slave address is internally programmed to 1100000. The eighth bit (R/W) following the 7-bit address determines whether a read or write operation will occur. The MAX2160/EBG continuously await a START condition followed by its slave address. When the device recognizes its slave address, it acknowledges by pulling the SDA line low for one clock period; it is ready to accept or send data depending on the R/W bit (Figure 1). Write Cycle When addressed with a write command, the MAX2160/EBG allow the master to write to a single register or to multiple successive registers. A write cycle begins with the bus master issuing a START condition followed by the seven slave address bits and a write bit (R/W = 0). The MAX2160/EBG issue an ACK if the slave address byte is successfully received. The bus master must then send to the slave the address of the first register it wishes to write to (see Table 1 for register addresses). If the slave acknowledges the address, the master can then write one byte to the register at the specified address. Data is written beginning with the most significant bit. The MAX2160/EBG again issue an ACK if the data is successfully written to the register. The master can continue to write data to the successive internal registers with the MAX2160/EBG acknowledging each successful transfer, or it can terminate transmission by issuing a STOP condition. The write cycle will not terminate until the master issues a STOP condition. Figure 2 illustrates an example in which registers 0 through 2 are written with 0x0E, 0xD8, and 0xE1, respectively.
MAX2160/MAX2160EBG
SLAVE ADDRESS S 1 1 0 0 0 0 0 R/W ACK P
SDA
SCL
1
2
3
4
5
6
7
8
9
Figure 1. MAX2160 Slave Address Byte
START
WRITE DEVICE ADDRESS 1100000
R/W 0
ACK
WRITE REGISTER ADDRESS 0x00
ACK
WRITE DATA TO REGISTER 0x00 0x0E
ACK
WRITE DATA TO REGISTER 0x01 0xD8
ACK
WRITE DATA TO REGISTER 0x02 0xE1
ACK STOP
Figure 2. Example: Write Registers 0 through 2 with 0x0E, 0xD8, and 0xE1, Respectively
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ISDB-T Single-Segment Low-IF Tuners MAX2160/MAX2160EBG
START
WRITE DEVICE ADDRESS 1100000
R/W 1
ACK
READ FROM STATUS BYTE-1 REGISTER
ACK
READ FROM STATUS BYTE-2 REGISTER
ACK/ NACK
STOP
Figure 3. Example: Receive Data from Read Registers
Read Cycle There are only two registers on the MAX2160/EBG that are available to be read by the master. When addressed with a read command, the MAX2160/EBG send back the contents of both read registers (STATUS BYTE-1 and STATUS BYTE-2). A read cycle begins with the bus master issuing a START condition followed by the seven slave address bits and a read bit (R/W = 1). If the slave address byte is successfully received, the MAX2160/EBG issue an ACK. The master then reads the contents of the STATUS BYTE-1 register, beginning with the most significant bit, and acknowledges if the byte is received successfully. Next, the master reads the contents of the STATUS BYTE-2 register. At this point the master can issue an ACK or NACK and then a STOP condition to terminate the read cycle. Figure 3 illustrates an example in which the read registers are read by the master.
bits in the control register (see Table 5 for a summary of attack point settings). The PWRDET pin output can be configured to provide either a voltage output (directly from the RMS powerdetector stage) or current output (default) through the diagnostic bits D[2:0] in the test register.
Closed-Loop RF Power Control
The default mode of the IF power detector is current output mode. Closed-loop RF power control is formed by connecting the PWRDET pin directly to the GC1 pin. A shunt capacitor to ground is added to set the closedloop response time (see the Typical Operating Circuit). The recommended capacitor value of 10nF provides a response time of 0.1ms. Closed-loop RF power control can also be formed using the baseband processor and the power detector in voltage output mode. In this configuration, the processor senses the power detector's output voltage and uses this information to drive the GC1 pin directly. Voltage output mode is enabled by setting the D[2:0] bits in the test register to 100. In voltage mode, the PWRDET pin outputs a scaled DC voltage proportional to the RF input power. For the RF input range of -62dBm to -48dBm, the DC output voltage ranges from 84mV to 420mV.
Applications Information
RF Input (RFIN)
The MAX2160/EBG are internally matched to 50 and requires a DC-blocking capacitor (see the Typical Operating Circuit).
RF Gain Control (GC1)
The MAX2160/EBG feature a variable-gain low-noise amplifier that provides 43dB of RF gain-control range. The voltage control (VGC1) range is 0.3V (minimum attenuation) to 2.7V (maximum attenuation).
High-Side and Low-Side LO Injection
The MAX2160/EBG allow selection between high-side and low-side LO injection through the HSLS bit in the control register. High-side injection is the default setting (HSLS = 1).
IF Power Detector
The MAX2160/EBG include a true RMS power detector at the mixer output. The power-detector circuit is enabled or disabled with the EPD bit in the control register. The attack point can be set through the PD[2:0]
Q-Channel Shutdown
The Q channel low-IF output of the MAX2160/EBG can be turned off with the QOFF bit in the XTAL divide register for use with single low-IF input demodulators (use I channel only). Turning off the Q channel reduces the supply current by approximately 3mA.
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ISDB-T Single-Segment Low-IF Tuners
IF Filter Tuning
The center frequency of the baseband bandpass filter is tuned to 571kHz during production at the factory. However, the factory-set trim may be bypassed and the filter's center frequency can be adjusted through the FLTS and TUN[2:0] bits in the test register. Setting the FLTS bit sets the filter's center frequency to the factoryset tuning, clearing the FLTS bit allows the filter's center frequency to be adjusted with the TUN[2:0] bits (see Table 2). During the selection process, the VASE bit in the STATUS BYTE-2 register is cleared to indicate the automatic selection function is active. Upon successful completion, bits VASE and VASA are set and the VCO and sub-band selected are reported in the STATUS BYTE-2 register (see Table 11). If the search is unsuccessful, VASA is cleared and VASE is set. This indicates that searching has ended but no good VCO has been found, and occurs when trying to tune to a frequency outside the VCO's specified frequency range.
MAX2160/MAX2160EBG
Fixed IF Gain Step
To maintain the best possible sensitivity for both QPSK and QAM signals, the MAX2160/EBG include a control bit (MOD) to increase the gain of the baseband stage by approximately 7dB. This gain step is intended to be used when receiving QPSK signals. Set the MOD bit to one in QPSK receive mode, set the MOD bit to zero in QAM receive mode.
Charge-Pump Select (CPS)
The MAX2160/EBG also allow for manual selection of the charge-pump current (CPS = 0) or automatic selection based on the final VTUNE ADC read value (CPS = 1). When in manual mode, the charge-pump current is programmed by bits CP[1:0] with the 2-wire bus. When in automatic selection mode, the CP[1:0] bits are automatically set according to the ADC table (see Tables 12 and 13). The selected charge-pump current (manually or automatically) is reported in the STATUS BYTE-1 register.
VCO Autoselect (VAS)
The MAX2160/EBG include four VCOs with each VCO having eight sub-bands. The local oscillator frequency can be manually selected by programming the VCO[1:0] and VSB[2:0] bits in the VCO register. The selected VCO and sub-band is reported in the STATUS BYTE-2 register (see Table 11). Alternatively, the MAX2160/EBG can be set to automatically choose a VCO and VCO sub-band. Automatic VCO selection is enabled by setting the VAS bit in the PLL register, and is initiated once the N-divider LSB register word is loaded. In the event that only the Rdivider register or N-divider MSB register word is changed, the N-divider LSB word must also be loaded (last) to initiate the VCO autoselect function. The VCO and VCO sub-band that are programmed in the VCO[1:0] and VSB[2:0] bits serve as the starting point for the automatic VCO selection process.
3-Bit ADC
The MAX2160/EBG have an internal 3-bit ADC connected to the VCO tune pin (VTUNE). This ADC can be used for checking the lock status of the VCOs. Table 13 summarizes the ADC trip points, associated charge-pump settings (when CPS = 1), and the VCO lock indication. The VCO autoselect routine will only select a VCO in the "VAS locked" range. This allows room for a VCO to drift over temperature and remain in a valid "locked" range. The ADC must first be enabled by setting the ADE bit in the VCO register. The ADC reading is latched by a subsequent programming of the ADC latch bit (ADL = 1). The ADC value is reported in the STATUS BYTE-2 register (see Table 11).
Table 12. Charge-Pump Current Selection
VAS 0 0 1 1 1 CPS 0 1 0 1 1 VASA X X X 0 1 CHARGE-PUMP VALUES (CP[1:0]) Values programmed with 2-wire bus Values selected by ADC read Values programmed with 2-wire bus Values programmed with 2-wire bus Values selected by ADC read
Table 13. ADC Trip Points, Associated Charge-Pump Settings, and Lock Status
VTUNE (VT) VT < 0.41V 0.41V < VT < 0.6V 0.6V < VT < 0.9V 0.9V < VT < 1.3V 1.3V < VT < 1.7V 1.7V < VT < 1.9V 1.9V < VT < VCC - 0.41V VCC - 0.41V < VT ADC[2:0] 000 001 010 011 100 101 011 111 CP[1:0] 00 00 00 01 10 11 11 11 LOCK STATUS Out of Lock Locked VAS Locked VAS Locked VAS Locked VAS Locked Locked Out of Lock
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ISDB-T Single-Segment Low-IF Tuners MAX2160/MAX2160EBG
Loop Time Constant Pin (LTC)
The LTC function sets the wait time for an ADC read when in VCO autoselect mode. The time constant is set by charging an external capacitor connected to the LTC pin with a constant current source. The value of the current source can be programmed to 1A or 2A with the LTC bit in the VCO register (see Table 4). The LTC time constant is determined by the following equation: Time constant = CLTC x 1.7 / ILTC where: CLTC = capacitor connected from the LTC pin to ground. ILTC = 1A (LTC = 0) or 2A (LTC = 1). Setting CLTC equal to 1000pF gives a time constant of 1.7ms with ILTC set to 1A and 0.85ms with ILTC set to 2A.
Shutdown and Standby Modes
The MAX2160/EBG feature hardware- and softwarecontrolled shutdown mode as well as a software-controlled standby mode. Driving the SHDN pin low with bit EPD = 0 places the device in hardware shutdown mode. In this mode, the entire device including the 2wire-compatible interface is turned off and the supply current drops to less than 10A. The hardware shutdown pin overrides the software shutdown and standby modes. Setting the PWDN bit in the XTAL divide register enables power-down mode. In this mode, all circuitry except for the 2-wire-compatible bus is disabled, allowing for programming of the MAX2160/EBGs' registers while in shutdown. Setting the STBY bit in the XTAL divide register puts the device into standby mode, during which only the 2-wire-compatible bus, the crystal oscillator, the XTAL buffer, and the XTAL buffer-divider are active. In all cases, register settings loaded prior to entering shutdown are saved upon transition back to active mode. Default register values are loaded only when VCC is applied from a no-VCC state. The various powerdown modes are summarized in Table 15. Supply current fluctuations for nondefault register settings are shown in Table 16.
ENTCXO
The MAX2160/EBG have both an integrated crystal oscillator and a separate TCXO buffer amplfier. The ENTCXO pin controls which reference source is used (see Table 14).
XTALOUT Divider
A reference buffer/divider is provided for driving external devices. The divider can be set for any division ratio from 1 to 31 by programming the XD[4:0] bits in the XTAL divide register (see Table 6). The buffer can be disabled by setting XD[4:0] to all zeros.
Diagnostic Modes and Test Pin
The MAX2160/EBG have several diagnostic modes that are controlled by the D[2:0] bits in the test register (see Table 2). The local oscillator can be directed to the TEST pin for LO measurements by setting the D[2:0] bits to all ones. In this mode, the supply current will increase by approximately 10mA. The TEST pin requires a 10k pullup resistor to VCC for proper operation.
Table 14. Reference Source Selection
ENTCXO VCC GND FUNCTION The TCXO input is enabled for use with an external TCXO The XTAL input is enabled for use with an external crystal
Table 15. Power-Down Modes
POWER-DOWN CONTROL MODE Normal Shutdown Power-Down Standby SHDN PIN VCC GND VCC VCC PWDN BIT 0 X 1 0 STBY BIT 0 X 0 1 SIGNAL PATH ON OFF OFF OFF CIRCUIT STATES 2-WIRE INTERFACE ON OFF ON ON XTAL ON OFF OFF ON DESCRIPTION All circuits active All circuits disabled 2-wire interface is active 2-wire interface, XTAL, and XTAL buffer/divider are active
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ISDB-T Single-Segment Low-IF Tuners MAX2160/MAX2160EBG
Table 16. Typical Supply Current Fluctuations for Nondefault Register Settings
MODE BIT CHANGE Default register settings QOFF = 1 (Q channel off) BBL[1:0] = 00 (lower linearity) BBL[1:0] = 01 (nominal linearity) Receive BBL[1:0] = 11 (high linearity) MOD = 1 (7dB baseband gain step enabled) EPD = 1 (power detector enabled) EPB = 0 (charge-pump prebias disabled) XD[4:0] = 00000 (XTALOUT buffer disabled) Shutdown Standby Power-Down SHDN = GND STBY = 1 PWDN = 1 TYPICAL ICC 46.5mA -- -- -- -- -- -- -- -- 1A 2.2mA 13.5A TYPICAL ICC FROM NOMINAL -- -3.3mA -2mA -1mA +1mA +0.3mA +1mA +5.1mA -40A -- -- --
Layout Considerations
The EV kit serves as a guide for PC board layout. Keep RF signal lines as short as possible to minimize losses and radiation. Use controlled impedance on all highfrequency traces. For proper operation of the TQFN package, the exposed paddle must be soldered evenly to the board's ground plane. Use abundant vias beneath the exposed paddle for maximum heat dissipation. Use abundant ground vias between RF traces to minimize undesired coupling. Bypass each VCC pin to ground with a 100pF capacitor placed as close to the pin as possible. In addition, the ground returns for the VCO, VTUNE, and charge pump require special layout consideration.
R21
The VCOBYP capacitor (C37) and the VCCVCO bypass capacitor (C19) ground returns must be routed back to the GNDVCO pin and then connected to the overall ground plane at that point (GNDVCO). All loop filter component grounds (C27-C30) and the VCCCP bypass capacitor (C17) ground must all be routed together back to the GNDCP pin. GNDTUNE must also be routed back to the GNDCP pin along with all other grounds from the PLL loop filter. The GNDCP pin must then be connected to the overall ground plane. Figure 4 shows a schematic drawing of the required layout connections. Refer to the MAX2160 evaluation kit for a recommended board layout.
R22 C29 C30
ROUTE GNDTUNE, C17, AND ALL LOOP FILTER COMPONENT GROUNDS TO GNDCP.
VCC C28
R20 C27 VCC ROUTE C19 AND C37 TO GNDVCO. C19
C17
CONNECT GNDCP TO THE BOARD'S GROUND PLANE.
CONNECT GNDVCO TO THE BOARD'S GROUND PLANE. C37
40 GNDCP
39 VCCCP
38 CPOUT
37 TEST
36 GNDTUNE
35 VTUNE
34 GNDVCO
33 VCCVCO
32 VCOBYP
Figure 4. Ground Return Layout Connections for the VCO, Charge Pump, and VTUNE ______________________________________________________________________________________ 21
ISDB-T Single-Segment Low-IF Tuners MAX2160/MAX2160EBG
Typical Operating Circuit
R21 C28 R20 C27 C29 R22 C30
VCC
VCC
C17 C37 GNDTUNE GNDVCO VCCVCO VCOBYP GNDCP VCCCP CPOUT VTUNE TEST
C19
N.C.
40 1
39
38
37
36
35
34 TANK
33
32
N.C. 31 30
N.C. VCCBB N.C. QOUT GNDBB
VCC
TCXO 2 XTAL VCC GNDXTAL VCCXTAL VCC C3 C4 BUFFERED CRYSTAL OUTPUT XTALOUT VCCDIG SDA R12 SERIAL-DATA INPUT/OUTPUT SERIAL-CLOCK INPUT VCC R13 SCL C18 LTC 3 4 5 6
FREQUENCY SYNTHESIZER
DIV4
ADC
29 28 27
C16 C22 QUADRATURE OUTPUT (OPTIONAL) IN-PHASE OUTPUT R18 VGC2 C15
/
26 25
C21 IOUT N.C. GC2 ENTCXO N.C.
C5
INTERFACE LOGIC AND CONTROL
7 8 9 10 N.C.
24
MAX2160
PWRDET EP
23 22 21
11
12 VCCBIAS
13 RFIN
14 SHDN
15 N.C.
16 VCCLNA
17 GC1
18 VCCMX
19 PWRDET
20 VCCFLT VCC
C12 C7 VCC
VCC
C9 RF INPUT ON SHDN OFF NOTE: SHOWN FOR TQFN PACKAGE. C14 C8 C10
Chip Information
TRANSISTOR COUNT: 23,510 PROCESS: BiCMOS
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ISDB-T Single-Segment Low-IF Tuners
Pin Configurations/Functional Diagrams (continued)
TOP VIEW
MAX2160/MAX2160EBG
41 VCCBB
32 VTUNE
30
26
23
20
16 CPOUT 10
1 GNDCP 2
VCOBYP VCCVCO GNDVCO GNDTUNE
42 GND
33 N.C.
VCCCP TCXO
MAX2160EBG+
29 N.C. 18 TEST 22 SHDN 19 LTC
11 XTAL
3 GND 4
43 QOUT 44 IOUT 45 N.C. 46 N.C. 47 GC2 40
GND
34 N.C. 35
12 13
VCCXTAL XTALOUT 5
N.C. ALIGNMENT MARK (NOT BUMPED) 36 N.C. 37 ENTCXO 38 PWRDET 39
VCCFLT
GND VCCDIG 14 SDA 15 GND 6 GND 7 SCL 8 GND
28 VCCMX 31
GND
25 GC1 24 21 17
RFIN VCCLNA GNDLNA
27
GND
9
VCCBIAS
WLP
______________________________________________________________________________________
23
ISDB-T Single-Segment Low-IF Tuners MAX2160/MAX2160EBG
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information go to www.maxim-ic.com/packages.)
E E/2
(NE-1) X e
k D/2
D
(ND-1) X e D2/2 e b E2/2 k
C L
C L
D2
L
E2
e L
C L C L
L1 L e e L
A1
A2
A
PACKAGE OUTLINE 36, 40, 48L THIN QFN, 6x6x0.8mm
21-0141
F
1
2
24
______________________________________________________________________________________
QFN THIN.EPS
ISDB-T Single-Segment Low-IF Tuners
Package Information (continued)
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information go to www.maxim-ic.com/packages.)
MAX2160/MAX2160EBG
NOTES: 1. DIMENSIONING & TOLERANCING CONFORM TO ASME Y14.5M-1994. 2. ALL DIMENSIONS ARE IN MILLIMETERS. ANGLES ARE IN DEGREES. 3. N IS THE TOTAL NUMBER OF TERMINALS. 4. THE TERMINAL #1 IDENTIFIER AND TERMINAL NUMBERING CONVENTION SHALL CONFORM TO JESD 95-1 SPP-012. DETAILS OF TERMINAL #1 IDENTIFIER ARE OPTIONAL, BUT MUST BE LOCATED WITHIN THE ZONE INDICATED. THE TERMINAL #1 IDENTIFIER MAY BE EITHER A MOLD OR MARKED FEATURE. 5. DIMENSION b APPLIES TO METALLIZED TERMINAL AND IS MEASURED BETWEEN 0.25 mm AND 0.30 mm FROM TERMINAL TIP. 6. ND AND NE REFER TO THE NUMBER OF TERMINALS ON EACH D AND E SIDE RESPECTIVELY. 7. DEPOPULATION IS POSSIBLE IN A SYMMETRICAL FASHION. 8. COPLANARITY APPLIES TO THE EXPOSED HEAT SINK SLUG AS WELL AS THE TERMINALS. 9. DRAWING CONFORMS TO JEDEC MO220, EXCEPT FOR 0.4mm LEAD PITCH PACKAGE T4866-1. 10. WARPAGE SHALL NOT EXCEED 0.10 mm. 11. MARKING IS FOR PACKAGE ORIENTATION REFERENCE ONLY. 12. NUMBER OF LEADS SHOWN FOR REFERENCE ONLY.
PACKAGE OUTLINE 36, 40, 48L THIN QFN, 6x6x0.8mm
21-0141
F
2
2
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 25 (c) 2005 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products, Inc.

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